1. Field of the Invention
The present invention relates to a technique of a semiconductor memory apparatus which is shared by multiple bus masters. In particular, the present invention relates to a memory access control system in which the multiple bus masters reads data from the semiconductor memory apparatus by using random priorities.
Priority is claimed on Japanese Patent Application No. 2007-121526, filed May 2, 2007, the content of which is incorporated herein by reference.
2. Description of the Related Art
In the past, in accordance with approaching steps of increasing the frequency of clocks of a microprocessor as much as possible in order to improve the ability of the microprocessor, fine processings in a semiconductor technology has been developed. As an adverse effect of such a development, the leak current of a transistor has been largely increased, and there is a problem of electric power consumption. Therefore, it has gradually been more difficult to improve the ability of the microprocessor by increasing the frequency of clocks of the microprocessor in the same manner as used in the past. In order to solve such a problem, there is a major solution for improving the ability of the microprocessor without increasing the frequency of clocks of the microprocessor by mounting multiple processor cores on one chip and conducting a distributed processing of tasks.
In a computer system conducting an information processing in parallel by using a CPU (central processing unit) providing such multiple cores, it is necessary to set a priority to each of the reading requests for reading a shared main memory in order to read the requested data at an appropriate time. Otherwise, ability of information processing cannot be improved.
In addition, in order to improve the efficiency of the memory bus between the CPU having the multiple cores and the main memory, it is preferable to control time of reading and writing data so as to avoid blanks or vacancy of data transfer of the memory bus. Therefore, it has been important to improve the flexibility of memory access by controlling both a memory reading request and a transfer request of the read data.
With regard to such a technique, there are the following Patent Documents 1-4. Patent Documents 1 and 2 disclose a memory access adjusting method and a circuit of this method in which if there is a conflict among memory access requests, each request is conducted in an order determined in accordance with the priority of each of the requests.
In addition, Patent Document 3 discloses a technique using a memory integrating apparatus in which a reservation is made when an operation request is accepted from each of the processing units, and a memory accessing means selects the reserved operation request based on the conditions and generates a memory accessing signal. Therefore, in Patent Document 3, each memory accessing operation corresponding to operational requests from the processing units is independently conducted, and conditions of reading/writing operations of one memory requested by the multiple processing units are improved.
Patent Document 4 discloses a technique of a DSP-memory data transmission apparatus applied to an apparatus which provides a CPU and multiple DSP (digital signal processor), and the technique includes: a transmission request selection circuit which receives transmission request signals from the CPU or DSP; and a transmission request maintaining circuit which receives and temporally maintains the transmission request signals and transmits command signals requesting transmission of data in accordance with the priority of the transmission request signal, wherein the DSP-memory data transmission apparatus which is connected to each of the multiple DSP via an expansion bus. The DSP-memory data transmission apparatus of Patent Document 4 further includes: an expansion bus control circuit which receives the command signals, reads transmission information of the CPU or the DSP and transmits data based on the transmission information; and a dual port RAM (random access memory) which maintains transmission data for the CPU, wherein the expansion bus control circuit reads or writes the transmission data stored in the dual port RAM. In accordance with the above-described constitution, Patent Document 4 discloses a technique of using the DSP-memory data transmission apparatus which can conduct data transmission operations between the multiple DSP and the memory by using circuits with simple constitutions.
As described above, control methods of Patent Documents 1-4 are generally known that conduct memory access operations when there is a conflict among reading requests of multiple information processing apparatuses such as CPU.    [Patent Document 1] Japanese Patent Application, First Publication No. H07-200488    [Patent Document 2] Japanese Patent Application, First Publication No. H08-16454    [Patent Document 3] Japanese Patent Application, First Publication No. 2002-55807    [Patent Document 4] Japanese Patent Application, First Publication No. 2003-76654
However, these prior arts have a problem such as a predetermined method of setting the priority, and that is, it is not possible to control the reading requests if the priority is changed every time the reading request is issued.
In addition, these prior arts have an assumption in which a memory access operation is conducted after determining the priority by a memory access control circuit, and the operation is suspended until the corresponding data is received. Therefore, the priors have another problem in which there is a possibility of exclusively using the memory bus from issuing a read request to reception of data.